Bus-based multiprocessor systems are commonly used in current architectures. Using a bus allows several processors or other devices (all of which may be called “agents” of the bus) to share system resources such as system memory and input/output (I/O) devices. An example of such a bus is the Front Side Bus (FSB) designed for use with Pentium® class compatible microprocessors such as those produced by Intel® Corporation. Generally only one of the processors or other agents may use the bus at a given time. If a single agent requests access to the bus, it may use it. However, often multiple agents request access to the bus at roughly the same time. In this case, a process of determining which agent may have access, called an “arbitration”, may be performed.
One form of arbitration, called priority arbitration, gives to priority agents the ability to issue a bus request that overrides other agents' bus requests. Priority arbitration may be useful for agents, such as I/O devices, that require quick access but not necessarily with high bandwidth requirements. Priority agents may use a relatively simple request and grant logic to gain access to the bus. Another form of arbitration, called symmetric arbitration, permits symmetric agents to arbitrate amongst themselves in a distributed fashion and grant bus access in a fair manner. This fair manner may include round-robin grants of access. Symmetric agents were originally so labeled because they contain state machines of a common design, therefore permitting them to decide among themselves which symmetric agent should next have bus access. Symmetric arbitration may be useful for agents, such as processors, that may have higher bandwidth requirements but may not need immediate access to the bus. Busses may support both priority arbitration and symmetric arbitration for various connected agents.
One difficulty that arises when using a bus using symmetric arbitration is that the number of symmetric agents may be limited. Special symmetric agent bus request lines may be used, and a limited number of these may be designed into a given bus environment. This limited number of symmetric agent bus request lines may be designed into the processors themselves. Therefore, in situations when it may be necessary to add just a single additional processor to such a system, the other processors and agents may need extensive redesign and manufacture. This may be unnecessarily costly and time consuming.